Digital transmission system

ABSTRACT

A digital transmission system which serves a multiplicity of subscribers by a multiplicity of channel units. Each channel unit serves up to two subscribers. At each end of the system, there is included a signaling processing unit (SPU) which provides both time slot interchanging and change in format for the signaling information. At each end of the system, there is another unit (TRU) which provides time slot interchanging for the nonsupervisory information for each subscriber. The channel units are arranged in channel banks for four groups of units each. Each channel bank is connected to the SPU by two single lines over one of which all the supervisory (signaling, provisioning and testing) information for the units in the bank is transmitted and over the other of which all the supervisory information from the units is transmitted. The TRU is connected to each group in the bank by a pair of lines.

This is a continuation of co-pending application Ser. No. 07/261,771filed on Oct. 24, 1988, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to digital loop carrier systems and moreparticularly to various circuits for use therein.

2. Description of the Prior Art

Digital loop carrier systems which provide service between amultiplicity of subscribers and a telephone central office are known.

Typically, one or more subscribers are served by an electronic circuit,sometimes known as a channel unit, which provides an interface betweenthose subscribers and the carrier system. Identical channel units arealso located at the central office end of the system. While the numberof subscribers served by each channel unit depends on the systemarchitecture, a typical system servicing N subscribers has M channelunits, where M is less than or equal to N.

Among the information sent by each subscriber to the central office andfrom the central office to the subscriber is that related to signaling.The central office must know whether each subscriber's telephone ison-hook or off-hook. The central office must send to the subscriber endof the system an indication relating to the ringing of each individualsubscriber's telephone when a call has been placed to the subscriberthrough the system.

In earlier digital loop carrier systems, the signaling information(on/off hook, ringing) was defined at the channel units. Signaling whichconveys information relating to on/off hook and ringing status requiresthe use of only two bits, i.e., four states. This type of signaling isknown in the telephone industry as A, B signaling. In one prior artdigital loop carrier system, the signaling information is sent to all ofthe channel units over a single line. Two other leads which are alsoconnected to all of the channel units identify the signaling informationas either A or B signaling. In addition, each of the channel units arephysically wired to a channel decode block, i.e. there are address lineswhich are physically wired to each channel unit.

Digital loop carrier systems have become increasingly complex. Thiscomplexity has allowed larger number of subscribers to be served by thesame system. Additional signaling state formats have been defined forthose new systems. Further changes in transmission format standards havecaused even more signaling state formats to be defined. Continuing todefine the signaling information at the channel units requires aspecially designed unit for each such defined signaling state format. Inthe context of the system described above, this also means that thechannel unit card have thereon the circuitry to decode and utilize theparticular signaling state format being used in the system.Alternatively, in that prior art system, it might be possible to designa single channel unit to be utilized with all known signaling stateformats but such a channel unit would be quite complex.

It is, however, desirable to design a carrier system which is capable ofuse with any one of a number of different transmission format standards.Rather than specifically design a channel unit for each such standard oralternatively try to design a channel unit which can interface with allknown standards, it is also desirable to have a system which is flexiblein that it can be used with any one of a number of different definedsignaling state formats. The carrier system of the present inventionallows for that flexibility in that there is included therein anadaptable signaling processing unit (SPU).

The increasing complexity of digital loop carrier systems has alsoallowed many different types of subscribers to be served by the samesystem. This means that such systems have a large number of differenttypes of channel units which can be inserted in the system in order toserve the subscriber. The particular type of channel unit inserteddepends on the service needed by the subscriber. In order to keep thenumber of different types of channel units within reason, the channelunits have the capability of being adjustable depending on thesubscriber's needs. That adjustability may for example relate to theamount of gain to be provided to the subscriber.

In the prior art digital loop carrier system described above, thesetting of those adjustable parameters can only be done in the field atthe time the channel unit is plugged in to the slot associated with thatsubscriber. Such setting of the adjustable parameters is known as"provisioning". In the known carrier system, that provisioning isprovided by making certain changes on the channel unit such as thesetting of various dip switches on the card or moving jumpers. For thatsystem, an installer is given an installation order indicating theparticular subscriber for which the card is to be inserted, the type ofcard and the provisioning therefor. The installer then drives to theremote location which services that subscriber. The installer then setsthe dip switches and inserts the card. The card must then be tested fromthe central office and in order for that to be done, the installer mustplace a telephone call to the office. As can be seen, the providing ofservice to new subscribers in the prior art digital loop carrier systemis very labor intensive.

It is, however, desirable to design a digital carrier system which hasthe ability to both provision and test the channel units from thecentral office. It is also desirable to provide that provisioning andtesting information to and from the particular channel unit over thesame path which is used to provide the signaling to the channel unit. Inorder to provide all of that information to and from the channel unit,it is necessary for the unit to receive and transmit several bytes. Asdescribed above, the prior art digital loop carrier system has separatelines for the A and B signaling. If that system were expanded in orderto be able to transmit and receive from the channel unit the multiplenumber of bits associated with the several bytes of information needed,then that system would include a large number of lines between eachchannel unit and the common circuitry at the subscriber end of thesystem. That is most undesirable. The digital transmission system of thepresent invention allows for that multiple amount of information to bereceived by and transmitted from each channel unit over only two signalpaths. In the system of the present invention those two paths are sharedby a multiplicity of channels.

It is also desirable to design a digital carrier system which includestherein the flexibility for interchanging time slots not only for thesignaling information but also for the encoded signals to and from thesubscribers of the system. Each subscriber is served by an associatedchannel of the system. There are several channel sequences in use today.The prior art digital loop carrier system is designed to work with onlyone of those sequences. In order for that system to "talk" to another ofthe known sequences it is necessary for that system to be provided witha map which relates the sequence for which it is designed to the othersequence. That system does not have the capability to change the channelsequence by interchanging time slots.

The digital transmission system of the present invention allows suchinterchanging of time slots to occur for not only the signalinginformation but also for the encoded signals to and from the subscribersof the system. This ability to interchange time slots allows the systemof the present invention to change its channel sequence so that it canbe used with any one of a number of different defined sequences. Thisability to interchange time slots also allows the system of the presentinvention to provide certain additional features, such as the ability totest one end of the system disconnected from the other end of thesystem, which the prior art digital loop carrier system is unable toprovide.

SUMMARY OF THE INVENTION

A digital transmission system which serves a multiplicity of subscribersby a multiplicity of channel units. The system has two terminals whichare interconnected to each other by transmission means.

The transmission means carriers supervisory information andnonsupervisory information for each of the channel units from one of theterminals to the other of the terminals and from the other terminal tothe one terminal. The one terminal includes a channel bank which has oneor more of the channel units. Each of the channel units are associatedwith a predetermined number of the subscribers served by the system.Interface circuitry is connected to the transmission means for receivingthe supervisory and nonsupervisory information from the other terminaland for transmitting to the other terminal the supervisory andnonsupervisory information from the one terminal. A first sign singlerdata line is connected between the interface circuitry and the onechannel bank. The first data line is for carrying from the interfacecircuitry to the one channel bank all of the supervisory informationfrom the other terminal for the channel bank and not for carrying fromthe interface circuitry to the channel bank any of the nonsupervisoryinformation from the other terminal for the channel bank. A second dataline is connected between the interface circuitry and the channel bank.The second single data line is for carrying from the channel bank to theinterface circuitry all of the supervisory information from that channelbank for the other terminal and not for carrying from the channel bankto the interface circuitry any of the nonsupervisory information fromthat channel bank for the other terminal.

The system also converts signaling state information received for all ofthe subscribers in one format to another format.

Each subscriber of the system has an associated predetermined format forsignaling information. The transmission means carriers for all of thesubscribers signalling information having for each subscriber anassociated format which may be different than the predetermined formatassociated with each subscriber. The one terminal has circuitry whichresponds to all of the received signaling information for translatingfor each of the subscribers the transmission means carried signalinginformation format associated with each of the subscribers to thesignaling information format associated with each of the subscribers.

In the system, each of the subscribers have an associated predeterminedtime slot for signaling information and an associated predetermined timeslot for nonsupervisory information. The transmission means between thetwo terminals carries all of the subscriber signaling and nonsupervisoryinformation. The transmission means carried signaling information hasfor each subscribers an associated time slot which may be different thanthe predetermined signaling information time slot associated with eachof the subscribers. The transmission means carried nonsupervisoryinformation has for each subscriber an associated time slot which may bedifferent than the predetermined nonsupervisory information time slotassociated with each of the subscribers. The one terminal has circuitrywhich responds to all of the received signaling and nonsupervisoryinformation for interchanging for all of the subscribers:

i) the transmission means carried signaling information time slotassociated with each of the subscribers to the predetermined signalinginformation time slot associated with each of the subscribers; and

ii) the transmission means carried nonsupervisory information time slotassociated with each of the subscribers to the predeterminednonsupervisory information time slot associated with each of thesubscribers.

The system also includes a multiplicity of channel units. Each unitserves a predetermined number of subscribers. Each channel unit includesa circuit which is responsive to the digital signals transmitted in thesystem for determining when supervisory information related to each ofthe subscribers served by that channel unit is occuring. That circuitryalso determines for which one of those served subscribers theinformation is for. That circuit then generates signals which areindicative of the occurrence of the information and the particularserved subscriber. The channel unit also includes interface circuitrywhich is connected to a first data line. That line carries thesupervisory information for all of the channel units connected to thatline. The interface circuitry is responsive to the indicative signalsand the digital signals for selecting from the data line only thesupervisory information related to the subscribers served by thatchannel unit.

DESCRIPTION OF THE DRAWING

FIG. 1 is a block diagram of the digital loop carrier system of thepresent invention.

FIG. 2 is a block diagram which shows in further detail certain parts ofthe system shown in FIG. 1.

FIG. 3 is a simplified block diagram of the signaling processing unit(SPU) of the system of the present invention.

FIG. 4a shows the manner in which the transmit/receive unit (TRU) of thesystem of the present invention is connected to the channel banks (CBs)of the system of the present invention.

FIG. 4b is a block diagram of the TRU.

FIG. 5a is a simplified block diagram of the interface circuitryincluded in each channel unit (CU) used in the system of the presentinvention.

FIG. 5b shows the waveforms for various signals associated with aparticular one of the CUs.

FIG. 5c shows a more detailed block diagram for the counter and decodecircuit included in the interface circuitry on each CU.

FIG. 5d shows a more detailed block diagram for the channel unit datalink interface circuit included in the interface circuitry on each CU.

FIG. 6 is a simplified block diagram for one embodiment of the serial toparallel and parallel to serial converter used in the LIUs, TRU and SPU.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, there is shown a block diagram of the digitalloop carrier system 10 of the present invention. System 10 providesservice between a multiplicity of subscribers (not shown) and atelephone central office (C.O.). System 10 is made up of a multiplicityof units located at both the subscriber end 12 and central office end 14of the system. As shown in FIG. 1, a unit which is located at thesubscriber end 12 has a corresponding functionally identical unitlocated at the central office end 14. Therefore, these units will bedescribed only with reference to the subscriber end 12 of system 10 withthe understanding that unless otherwise indicated the same descriptionholds for the central office end 14.

System 10 includes a multiplicity of channel units (CUs) 16 which areused to provide an interface for the analog signals received by andtransmitted from the subscribers. The number of channel units 16 insystem 10 depends upon the number of subscribers 12 served by thesystem. In general, a particular channel unit 16 can serve either one ortwo subscribers. The channel units are connected to transmit/receiveunit (TRU) 18 which is used to provide an interface between the order inwhich pulse code modulation (PCM) signals representing voice frequencytransmissions are sent to and from the CUs 16 and the order in whichthose signals are transmitted to or received from C.O. end 14 of system10.

System 10 further includes signal processor unit (SPU) 20 which as willbe described in more detail hereinafter is designed in a manner suchthat it has the capability of storing the signaling state formatsassociated with all of the CUs 16. In addition thereto, SPU 20 isdesigned so that it also has the capability of storing the provisioninginformation associated with all of the CUs 16. SPU 20 is connected tothe CUs 16 by only two data lines, one of which is associated withprovisioning, signaling as well as testing information to be sent to theCUs and the other of which is associated with provisioning, signaling aswell as testing information to be sent from the CUs. The signaling,provisioning and testing information is also known as the supervisoryinformation and will be so referred to at various places hereinafter.SPU 20 has the capability to, on a periodic basis, refresh theprovisioning and signaling information in each of CUs 16 and alsoprovide testing information as required. Finally, SPU 20 has thecapability to continually receive from central office 14 newprovisioning, signaling and, as necessary, testing information for eachof CUs 16.

System 10 further includes central processing unit (CPU) 22 which isused to provide control for both TRU 18 and SPU 20. The system furtherincludes a multiplicity of line interface units (LIUs) 24a to 24m whichare connected to the multiplicity of digital transmission lines 26a to26m. The digital transmission lines interconnect the subscriber end 12of system 10 with the central office end 14. LIUs 24a to 24m, as will bedescribed hereinafter, provides the interface between the encodedsignals on lines 26a to 26m to or from C.O. end 14. More specifically,LIUs 24a to 24m separate signaling information from the PCM signalsrepresenting voice frequency transmissions in the signals received onlines 26a to 26m from C.O. end 14 and combine the signaling informationwith the PCM signals representing voice frequency transmissions in thesignals to be transmitted on lines 26a to 26m to C.O. end 14.

Referring now to FIG. 2, there is a block diagram which shows in furtherdetail CUs 16, SPU 20, CPU 22 and LIUs 24a to 24m of system 10. Asdescribed above, system 10 can serve a multiplicity of subscribers. EachCU 16 may serve either one or two of those subscribers. System 10 mustthen include a multiplicity of CUs 16. The CUs may be arranged in amultiplicity of channel banks (CBs) 28a to 28m each capable of holdingthe same total number of CUs 16. The CUs 16 in each of channel banks 28ato 28m may be arranged in a multiplicity of equal groups, for example,the four groups 16a, 16b, 16c and 16d of FIG. 2. For ease of explanationhereinafter it will be assumed that each of CBs 28a to 28m has four suchequal groups. The equal groups 16a, 16b, 16c and 16d in each of channelbanks 28a to 28m will be referred to hereinafter as digroups A, B, C andD, respectively. For ease of illustration, only the digroups in channelbank 28a have been shown in FIG. 2.

Connected between SPU 20 and each of the CBs 28a to 28m are theassociated pairs of lines in the two groups of data lines 30a to 30m and31a to 31m. Line pair 30a, 31a are associated with CB 28a, line pair30b, 31b are associated with CB 28b etc. As all of the line pairsfunction in an identical manner only the function of line pair 30a, 31aneed be described hereinafter. That is only the line pair 30a, 31aassociated with all of the CUs 16 in CB 28a will be described, it beingunderstood that the other line pairs 30b, 31b; to 30m, 31m function inexactly the same manner with respect to all of the CUs 16 in theassociated one of the CBs 28b to 28m. As used hereinafter the term CUs16 unless indicated otherwise will refer only to the CUs 16 in CB 28a itbeing understood that the CUs 16 in the associated one of the CBs 28b to28m function in exactly the same manner.

One line 30a of line pair 30a, 31a is used to carry signaling,provisioning and testing information, i.e. supervisory information fromSPU 20 to all of the CUs 16 in CB 28a. The line 30a will be referred tohereinafter as the receive channel unit data link (RCUDL). The otherline 31a of pair 30a, 31a is used to carry signaling, provisioning andtesting information, i.e. supervisory information, from all of the CUs16 in CB 28a to SPU 20. That line 31a will be referred to hereinafter asthe transmit channel unit data link (TCUDL). The terms "transmit" and"receive" are defined with respect to the direction of information flowto or from the subscriber end 12 from or to the central office end 14,i.e., end 12 transmits information to end 14 and receives informationtherefrom.

Referring now to FIG. 3, there is shown a simplified block diagram ofSPU 20. SPU 20 may be divided into a receive signaling path 20a and atransmit signaling path 20b. As with FIG. 2, the terms "transmit" and"receive" as used herein are defined with respect to information flow toor from end 12 from or to end 14. The paths 20a and 20b include a numberof random access memories (RAMs) whose function will be described inmore detail hereinafter. The information necessary to address thelocations in all of those RAMs originates from CPU 22. For ease ofillustration, the various address busses associated with CPU 22 areshown in simplified from in FIG. 3.

As described above, SPU 20 must send to all of the CUs 16 in CB 28asignaling, provisioning and testing information. That information isreceived at SPU 20 from the C.O. end 14 of system 10 through theassociated one of LIUs 24a to 24m. That information is sent to CB 28aover the RCUDL 30a. Receive signaling path 20a of SPU 20 includes dataRAM 30, connection RAM 32, translation RAM 34, and channel unit datalink (CUDL) RAM 36 all of which work in conjunction with CPU 22 to sendthat information to CB 28a. Receive signaling path 20a also includesparallel to serial converter 37 which connects the output of CUDL RAM 36to RCUDL 30a.

Also as described above, all of the CUs 16 in CB 28a transmit to SPU 20signaling, provisioning and testing information. In turn, SPU 20transmits that information to the C.O. end 14 of system 10. Moreparticularly, SPU 20 obtains that information from CB 28a over the TCUDL31a. Transmit signaling path 20b of SPU 20 includes channel unit datalink (CUDL) RAM 38, connection RAM 40 and translation RAM 42 all ofwhich work in conjunction with CPU 22 to transmit that informationthrough the associated one of LIUs 24a to 24m to C.O. end 14. Transmitsignaling path 20b also includes serial to parallel converter 39 whichconnects TCUDL 31a to the input of CUDL RAM 38.

As described above, LIUs 24a to 24m are connected to C.O. end 14 by amultiplicity of digital transmission lines 26a to 26m. As is well knownin the art, those digital transmission lines carry in a predeterminedformat encoded signaling information either to or from the CUs 16 ofsystem 10. Provisioning and testing information is transmitted to C.O.end 14 or received therefrom by various means depending on the digitaltransmission format used in system 10. For example, if system 10 is ofthe type which uses the extended superframe format (ESF) then there isincluded in the digital signals on transmission lines 26a to 26m anembedded operations channel over which the provisioning and testinginformation is carried. If system 10 is not of the ESF type, thentesting information is transmitted to and received from C.O. end 14 overa separate link. That link may be of the kind disclosed in U.S. Pat. No.4,270,030. In any case, no matter how provisioning and testinginformation is received at SPU 20 from C.O. end 14 or transmittedthereto, it always passes through LIUs 24a to 24m. There are presently anumber of well-defined signaling state formats and system 10 has thecapability of adapting to any one of them. As will be described in moredetail hereinafter, that adaptability arises from the design of SPU 20and more particularly the use of translation RAM 34 in receive signalingpath 20a and translation RAM 42 in transmit signaling path 20b.

Also, as is well known in the art, the information for each CU 16carried on transmission lines 26a to 26m has its own time slot each ofwhich is associated with a particular one of the subscribers of system10. It is, however, desirable for system 10 to have the ability tointerchange time slots as needed. In other words, there is not anunalterable one to one correspondence between a particular time slot anda particular subscriber. This ability to interchange time slots for thesignaling information is also contained in SPU 20 and more particularlyin connection RAM 32 of receive signaling path 20a and connection RAM 40of transmit signaling path 20b. The circuitry necessary to interchangetime slots for the PCM signals representative of voice frequencyinformation is included in TRU 18 as will be described in more detailbelow.

As has been previously described, system 10 can serve a multiplicity ofsubscribers. Each of CUs 16 can serve one or two subscribers. Quitetypically, when system 10 is first put into service the number ofsubscribers being served is well below the capacity of system 10. Asmore subscribers are added to system 10, additional CUs 16 are added tosystem 10. In addition, while subscribers may have various levels ortypes of service it is desirable for a limited number of different CUs16 to be useable to provide those various levels or types of service.System 10 has the ability, from C.O. end 14, to "tell" a newly or evenpreviously connected CU 16 the level or type of service it is toprovide. Depending on the capability of the CU 16, it may not benecessary to physically remove and replace an already installed CU ifthe level of service to the subscriber(s) it serves is changed. Thatability also resides in SPU 20 and more particularly in connection RAM32 of receive signaling path 20a and connection RAM 40 of transmitsignaling path 20b.

It is also desirable to test from C.O. end 14 the CUs 16. SPU 20 allowssystem 10 to have that capability. More particularly, it is CUDL RAM 36of receive signaling path 20a and CUDL RAM 38 of transmit signaling path20b which, respectively, receive from C.O. end 14 information fortesting CUs 16 and transmit to C.O. end 14 information relating to theresults of those tests.

A detailed description of the operation of SPU 20 will now be given.Receive signaling path 20a will first be described and then transmitsignaling path 20b.

As described above, the signaling information is received by LIUs 24a to24m from C.O. end 14 over transmission lines 26a to 26m. Thatinformation is written into data RAM 30. The address of the particularlocation in RAM 30 in which the signaling information is written isdetermined by CPU 22. The signaling information also includes someinformation which may be classified as "testing" information. For easeof discussion all of the information that is written into data RAM 30will be referred to hereinafter as signaling information. Theprovisioning and testing information is also received by LIUs 24a to 24min the manner described above. That information is then sent to CPU 22.

System 10 has a multiplicity of time slots, a multiplicity of LIUs 24ato 24m and a multiplicity of CUs 16. All of the CUs 16 in system 10 havetheir own unique address. That address is determined by the particularone of CBs 28a to 28m that the CU is associated with and the particularcard slot in that CB into which the card is placed. Each of the cardslots in each of the four digroups A, B, C, D of each of CBs 28a to 28mhas its own unique physical address. As each of CUs 16 is first placedin a card slot at subscriber end 12, provisioning information is sent toSPU 20 from the C.O. end 14. Among other things, that provisioninginformation identifies the CU 16 with a particular one of themultiplicity of time slots and LIUs 24a to 24m. That part of theprovisioning information is stored in connection RAM 32 in the form of alookup table.

As described above, data RAM 30 stores the signaling informationreceived from C.O. end 14. The signaling information may be in any oneof a number of known formats or even in a format which was created afterthe installation of system 10. The signaling information is sent to allof the CUs 16 in CB 28a. Each CU in CB 28a responds only to that part ofthe signaling information which is associated with that CU. As will bedescribed in more detail hereinafter in connection with FIGS. 5a to 5dthere is a unique time slot for signaling, provisioning and testinginformation associated with each CU 16 in CB 28a. Each CU 16 uses itsphysical address as well as several timing signals to determine theoccurrence of its time slot.

There is provided in translation RAM 34 a lookup table which translatesthe signaling information received from C.O. end 14 to the formnecessary to be sent to the CUs 16 over RCUDL 30a. The information whichis stored in the lookup table in translation RAM 34 comes from theprovisioning information sent by C.O. end 14. As each CU 16 is connectedin system 10, CPU 22 takes that part of the provisioning informationwhich relates to signaling translation and places it in translation RAM34. Under the control of CPU 22, the testing information is placeddirectly in CUDL RAM 36.

Also under the control of CPU 22 the signaling, provisioning and testinginformation to be sent over RCUDL 30a to all of the CUs 16 is assembledin CUDL RAM 36. That information is sent to the CUs 16 as a serial bitstream having a predetermined sequence. Parallel to serial converter 37converts the parallel bit stream used in receive signaling path 20a tothe serial bit stream to be sent over RCUDL 30a to all of the CUs 16.

The signaling information to be stored in data RAM 30 is received fromC.O. end 14 as part of the digitally encoded signal sent from the C.O.There is a unique location or time slot in that signal for eachsubscriber to system 10. The signaling information is written into dataRAM 30 in the order of receipt, which may not be the order of itstransmission to CUs 16. That order, as described in more detail below,is determined by the provisioning information stored in connection RAM32. In effect, data RAM 30 then acts as a buffer in that signalinginformation can be received from C.O. end 14 in a first order of timeslots and sent to CUs 16 in a second order of time slots which may bethe same as or different from the first time slot order.

The manner in which the provisioning information stored in the lookuptable of connection RAM 32 functions to determine the interchanging oftime slots will now be described. As CPU 22 addresses each location ofthe lookup table in connection RAM 32, the information stored therein isread out. Part of that information is used to address a unique locationin data RAM 30. That location has stored in it the signaling informationreceived for a particular one of the subscribers of system 10 from C.O.end 14. It should now be clear that by changing the information storedin connection RAM 32 another and different location in data RAM 30 canbe addressed in place of the location previously addressed during thelast occurrence of this time interval.

The signaling information stored in the addressed location is read outof data RAM 30 and is used in combination with the remaining bits of theinformation previously read out of the connection RAM 32 to address aunique location in translation RAM 34. That location has stored in itthe signaling information to be sent to the CUs 16 in that time slot. Itis that signaling information which is read out of translation RAM 34and stored in CUDL RAM 36 for subsequent transmission to all of the CUs16. The location in CUDL RAM 36 in which the information is storedidentifies it with a particular time slot, i.e. particular CU 16 andtherefore with a particular one of CBs 28a to 28m and the associated oneof RCUDL's 30a to 30m.

It should be appreciated that it is the provisioning information inconnection RAM 32 which determines the particular time slot in which thesignaling information for one of the subscribers of system 10 is to besent to all of the CUs 16. It should also be appreciated that it is thecombination of the provisioning information stored in connection RAM 32and the signaling information received from C.O. end 14 which determinesby addressing a location in translation RAM 34 the particular signalinginformation to be sent to all of the CUs 16 in that time slot. Thesignaling information received from C.O. end 14 is not sent directly toCUs 16.

It is this interaction between RAMs 30 and 32 which allows receivesignaling path 20a of SPU 20 to provide time slot interchanging for thesignaling information. It is the interaction between the informationstored in RAMs 30 and 32 as well as RAM 34 which allows receivesignaling path 20a of SPU 20 to have the capability of adapting to anyone of a wide variety of signaling formats which may be used in system10.

It should be further appreciated that while signaling information issent continuously from C.O. end 14 to SPU 20 that provisioning andtesting information is sent only as needed. Generally, provisioninginformation is provided only at the time when a CU 16 is first connectedto system 10. Thereafter, the provisioning information may be changedif, for example, it is desirable to interchange the time slots. As faras testing information is concerned, that is provided only when C.O. end14 wishes to test the CUs 16. It should, however, be appreciated thatSPU 20 continuously sends signaling information to all of the CUs 16 andin addition, also continuously sends provisioning information to all ofthe CUs 16. That "new" provisioning information is available for use ineach of the CUs 16 for a limited period of time. The provisioninginformation last sent is either refreshed if unchanged or updated ifchanged by the new provisioning information.

In summary then, a signal having a multiplicity of time slots eachassociated with a respective one of the CUs 16 is continually sent toall of the CUs 16 over RCUDL 30a by SPU 20. That signal contains updatedsignaling information received from C.O. end 14; provisioninginformation for either refreshing the provisioning information last sentto CUs 16 or for updating that information if the provisioninginformation has changed; and testing information received from C.O. end14 when testing is to be performed on one or more of CUs 16. As will beset forth in more detail hereinafter the particular time slot associatedwith each CU 16 is determined solely by the physical location of the CUin the digroups of CB 28a. Therefore, while all of the CUs 16 receivethe signal on RCUDL 30a, each CU reacts only to that part of the signalwhich is in its associated time slot.

Transmit signaling path 20b of SPU 20 will now be described. Itfunctions in a manner similar to receive signaling path 20a.

The CUs 16 transmit information relating to signaling, provisioning andtesting to SPU 20 over TCUDL 31a. That information is transmitted to SPU20 as a serial bit stream having a predetermined time slot sequence.Serial to parallel converter 39 converts the serial bit stream on TCUDL31a to the parallel bit stream used on transmit signaling path 20b.

The information is stored in CUDL RAM 38. The location in CUDL RAM 38 inwhich the information is stored is determined by the physical locationof the particular CU 16 from which it was sent. That storage locationnot only identifies it with having been sent from a particular CU 16 butalso with one of CBs 28a to 28m and the associated one of TCUDLs 31a to31m. As with connection RAM 32, connection RAM 40 includes a lookuptable which gives the particular one of the multiplicity of time slotsin the digital signal transmitted to C.O. end 14 and multiplicity ofLIUs 24a to 24m which are associated with a respective one of themultiplicity of CUs 16. The signaling information transmitted from CUs16 must be translated into the particular format being used in system10. That translation is provided by the lookup table contained intranslation RAM 42.

As with receive signaling path 20a the information stored in the lookuptable of connection RAM 40 and in the lookup table of translation RAM 42both come from the provisioning information. As described for connectionRAM 32, the provisioning information stored in the lookup table ofconnection RAM 40 functions to determine the interchanging of time slotsbetween those in the signal on TCUDL 31a and those in the signal to betransmitted to C.O. end 14. In this regard CUDL RAM 38 acts as a bufferin a manner similar to that described above for data RAM 30.

More specifically as CPU 22 addresses each location in the connectionRAM 40 lookup table the information stored therein is read out. Part ofthat information is used to address a unique location in CUDL RAM 38.The signaling information stored in the addressed location is then readout in an order determined by the provisioning information stored inconnection RAM 40. That signaling information is used in combinationwith the remaining bits of the information previously read out ofconnection RAM 40 to address a unique location in translation RAM 42.That location has stored in it the signaling information for one of thesubscribers which is to be sent to C.O. end 14 in that time slot.

It is this interaction between RAMs 38 and 40 which allows transmitsignaling path 20b of SPU 20 to provide time slot interchanging for thesignaling information. It is the interaction between the informationstored in RAMs 38 and 40 as well as RAM 42 which allows transmitsignaling path 20b of SPU 20 to have the capability of adapting to thewide variety of signaling states which may be used in system 10.

Therefore, SPU 20 has the capability of adapting to the wide variety ofsignaling states which may be used in system 10. SPU 20 also has thecapability of interchanging signaling time slots as desired. Finally,SPU 20 allows provisioning information to be sent from C.O. end 14 toCUs 16 so that the CUs can be provisioned from the central office asdesired.

As previously described in connection with FIG. 1, TRU 18 provides aninterface between the PCM signals representing voice frequencytransmissions to and from the CUs 16 and the order in which thosesignals are transmitted to or received from C.O. end 14. Therefore,prior to describing CUs 16 in more detail it is first necessary to morefully describe TRU 18.

As shown in simplified form in FIG. 4a, TRU 18 is connected to each ofthe four digroups in each of CBs 28a to 28m by the associated pairs oflines in the two groups of data lines 62a (1 to 4) to 62 m (1 to 4) and64a (1 to 4) to 64m (1 to 4). Line pair 62a (1), 64a (1) are associatedwith digroup A of CB 28a, line pair 62a (2), 64a (2) are associated withdigroup B of CB 28a etc. Lines 62a (1 to 4) to 62m (1 to 4) are used tocarry PCM signals received from C.O. end 14 to the CBs 28a to 28m. Lines64a (1 to 4) to 64m (1 to 4) are used to carry PCM signals to betransmitted from CBs 28a to 28m to C.O. end 14.

As all of the line pairs function in an identical manner only thefunction of line pairs 62a (1 to 4), 64a (1 to 4) need be describedhereinafter. That is only the line pairs associated with the fourdigroups A, B, C, D in CB 28a will be described it being understood thatthe other line pairs function in exactly the same manner with respect tothe associated one of the digroups in the associated one of CBs 28b to28m. In a manner similar to the description of SPU 20 the term CUs 16when used hereinafter, unless otherwise indicated will refer only to theCUs in the four digroups of CB 28a.

Referring now to FIG. 4b there is shown a block diagram for TRU 18. TRU18, as was the case with SPU 20, may be divided into a receive path 18aassociated with the PCM signals received from C.O. end 14 and a transmitpath 18b associated with the PCM signals to be transmitted to C.O. end14. The receive path 18a includes data RAM 50, connection RAM 52 andparallel to serial converter 54. The transmit path 18b includes serialto parallel converter 56, data RAM 58 and connection RAM 60. As was thecase with FIG. 3 the various address busses associated with CPU 22 areshown in simplified form in FIG. 4a.

The PCM signals are received from the C.O. end 14 and transmittedthereto in a predetermined time slot order. That order may be differentfrom or the same as the order in which those signals are sent to or fromthe CUs 16. It is the combination of RAMs 50 and 52 in receive path 18aand RAMs 58 and 60 in transmit path 18b which allow TRU 18 tointerchange those time slots for the PCM signals received from C.O. end14 and the PCM signals to be transmitted to C.O. end 14, respectively.The interchanging of the time slots is accomplished in accordance withthe provisioning information stored in lookup tables in RAMs 52 and 60in the same manner as was described for the signaling information timeslot interchanging provided by SPU 20.

The PCM signals are received from C.O. end 14 by LIUs 24a to 24m and aresent to TRU 18 in the form of a parallel bit stream. They are writteninto data RAM 50 and stored in a location therein determined by theorder in which they are received. CPU 22 addresses each location of thelookup table in connection RAM 52 and the provisioning informationstored therein is read out. As with SPU 20, part of that information isused to address a location in data RAM 50. That location has stored init the PCM signal for one of the subscribers of system 10. Theprovisioning information uniquely identifies that location in RAM 50 andthe information stored therein with that subscriber. The CU for thatsubscriber has a unique address determined by the particular one of CBs28a to 28m, the particular digroup A, B, C or D in that CB and the cardslot in that digroup in which it is located.

The PCM signal is sent to the CUs 16 in CB 28a over the associated oneof data lines 62a (1 to 4) in a serial bit stream. Parallel to serialconverter 54 provides the necessary conversion. The remaining bits inthe provisioning information are used to route the PCM signal over theassociated one of lines 62a (1 to 4).

It should be appreciated that the provisioning information stored in RAM52 determines the interchanging of time slots between those in the PCMsignal received from C.O. end 14 and those in the PCM signal to be sentto the CUs in each digroup of CB 28a. In this regard data RAM 50 acts asa buffer.

The PCM signals to be transmitted to C.O. end 14 from the CUs 16 in eachdigroup in CB 28a arrive at TRU 18 in the form of a serial bit streamhaving a predetermined time slot sequence over the associated one ofdata lines 64a (1 to 4). Serial to parallel converter 56 provides thenecessary conversion so that the PCM signals are in the parallel bitstream used in transmit path 18b.

The PCM signals are stored in data RAM 58. The particular location indata RAM 58 in which the information is stored is determined by CPU 22and identifies it as having been sent to TRU 18 from a particular one ofthe CUs 16 and digroups in CB 28a and therefore with the associated oneof the data lines 64a (1 to 4). Connection RAM 60 includes a lookuptable which gives the particular one of the multiplicity of time slotsin the digital signal transmitted to C.O. end 14 and multiplicity ofLIUs 24a to 24m which are associated with that particular CU 16.

As with receive path 18a the information stored in the lookup table ofconnection RAM 60 comes from the provisioning information. As describedfor connection RAM 52, the provisioning information stored in the lookuptable of connection RAM 60 functions to determine the interchanging oftime slots between those in the PCM signals on the associated one oflines 64a (1 to 4) and those in the signals to be transmitted to C.O.end 14. In this regard data RAM 58 acts as a buffer in a manner similarto that described above for data RAM 50.

More specifically, as CPU 22 addresses each location in the connectionRAM 60 lookup table the information stored therein is read out. Part ofthat information is used to address a unique location in data RAM 58.The PCM signal stored in the addressed location is then read out in anorder determined by the provisioning information stored in connectionRAM 60. It is this interaction between RAMs 58 and 60 which allowstransmit path 18b of TRU 18 to provide time slot interchanging for thePCM signals.

In summary, TRU 18 has the capability of interchanging PCM signal timeslots as desired. Now that TRU 18 has been fully described it ispossible to describe CUs 16 in more detail.

As described previously system 10 includes a multiplicity of CUs 16. ACU 16 may, depending on the configuration of system 10, serve either oneor two subscribers. In addition, the particular type of CU 16 used toserve the one or two subscribers depends on the service needed by thosesubscribers. Therefore, in a given configuration system 10 may includemany different types of CUs 16.

All of the CUs 16 must, however, interface with the associated ones ofRCUDL 30a to 30m and TCUDL 31a to 31m as well as interface with theassociated ones of lines 62a (1 to 4) to 62m (1 to 4) and 64a (1 to 4)to 64m (1 to 4). To that extent each of the CUs 16 must includeidentical circuitry for interfacing with those lines. That circuitrywill be described in connection with FIGS. 5a to 5d.

Before describing that circuitry the flow of the signaling, provisioningand testing information to and from the CUs 16 from and to SPU 20 overdata lines 30a to 30m and 31a to 31m will first be described. As thedata lines are arranged in pairs, each pair associated with a respectiveone of CBs 28a to 28m, and are otherwise identical it will only benecessary to describe the flow of information over line pair 30a, 31a.

Signaling, provisioning and testing information is sent to the CUs 16 bySPU 20 over RCUDL 30a and received therefrom over TCUDL 31a continuouslyin the form of a serial bit stream. A predetermined number of bytes areassociated with the information sent to and received from each of theCUs for each of the up to two subscribers served by that CU. Forexample, there may be six bytes associated with that information foreach subscriber. As each of the CUs 16 in digroups A, B, C, D of CB 28acan serve up to two subscribers they will each periodically receive andsend two groups of six bytes, i.e. twelve bytes in total, of signaling,provisioning, and testing information. Where the CU serves twosubscribers, six of those bytes will be associated with one of thosesubscribers and the other six bytes will be associated with the other ofthose two subscribers. Where the CU serves only one subscriber alltwelve bytes may contain information for that subscriber.

The order in which those bytes are sent to or from SPU 20 to the CUs 16in the digroups of CB 28a is primarily a matter of design choice. Forexample, if each digroup serves up to 24 channels, i.e. has up to 12 CUcards, then the six bytes may be sent in the following sequence:

i) byte 1 of channel 1 in digroup A followed by byte 1 of channel 2 inthat digroup etc. so that byte 1 is sent to all 24 channels in thedigroup;

ii) byte 2 of channel 1 in digroup A followed by byte 2 of channel 2 inthat digroup etc. so that byte 2 is sent to all 24 channels in thatdigroup;

iii) bytes 3, 4, 5 and 6 for all of the channels in digroup A are thensent in the manner described above for bytes 1 and 2;

iv) the six bytes for all the channels in digroup B are then sent in thesequence described in i) to iii) above followed by the six bytes for allthe channels in digroups C and D all sent in that same sequence.

The sequence is then repeated in the manner set forth in i) to iv)above.

Referring to FIG. 5a there is shown a simplified block diagram of thecircuit 66 included in each CU 16 for interfacing that CU with theassociated ones of RCUDLs 30a to 30m and TCUDLs 31a to 31m as well asthe associated ones of receive data (PCM) lines 62a (1 to 4) to 62m (1to 4) and transmit data (PCM) lines 64a (1 to 4) to 64m (1 to 4). Forease of description hereinafter it will be assumed that circuit 66 is ona CU 16 which is located in digroup A of CB 28a and that the CU servesthe subscribers connected to the first and second channels of thatdigroup. It will also be assumed that the digroup serves 24 channels andthat there are three other digroups in CB 28a each of which also serve24 channels. CU 16 is then connected to RCUDL 30a, TCUDL 31a, receivePCM line 62a (1) and transmit PCM line 64a (1).

Circuit 66 includes counting and decode circuit 68, PCM interfacecircuit 70 and CUDL interface circuit 72. Each of the circuits 68, 70,72 will be described in connection with the waveforms shown in FIG. 5b.Circuits 68 and 72 will then further be described in connection withFIGS. 5c and 5d, respectively as well as FIG. 5b.

PCM interface circuit 70 is connected to both receive data line 62a (1)which has the PCM signals received from C.O. end 14 for the twosubscribers served by CU 16 and transmit data line 64a (1) which has thePCM signals to be transmitted to C.O. end 14 from those two subscribers.To aid in the explanation of circuit 66 the receive PCM signals on line62a (1) are labeled as RPCM and the transmit PCM signals on line 64a (1)are labeled as TPCM in FIG. 5a. CUDL interface circuit 72 is connectedto both RCUDL 30a and TCUDL 31a.

Circuits 68, 70, 72 are all connected to receive a clock (CLK) signal.The CLK signal as shown in FIG. 5b is a periodic signal having a squarewaveform. It occurs at the rate of 1.544 Mbps. That is the rate at whichsignals are transmitted on digital transmission lines 26a to 26m.

Subscriber end 12 of system 10 should remain synchronized with C.O. end14. The central office has a clock signal which is part of the signalsreceived at subscriber end 12 on lines 26a to 26m. LIUs 24a to 24minclude a circuit for recovering, in a manner well known in the art, thecentral office clock signal. One of those recovered clock signals maythen be selected for connection to a phase-locked loop (PLL) located atsubscriber end 12. The PLL locks on to the recovered central officeclock in a manner well known in the art to thereby generate the CLKsignal. Alternatively, the CLK signal may be generated by a localoscillator located at the subscriber end 12. This allows for a CLKsignal even if subscriber end 12 is disconnected from C.O. end 14. Inthe system 10 of the present invention, the PLL and local oscillator arelocated in TRU 18.

Circuits 68 and 72 are also connected to receive a synchronizing (SYNC)signal. The SYNC signal is shown in FIG. 5b and occurs once every three(3) milliseconds. The SYNC signal is generated at subscriber end 12 bydividing the recovered central office clock by 4,632. The SYNC signalresets the counters contained in circuit 68 to thereby provide astarting point for the next interchange of signaling, provisioning andtesting information between SPU 20 and all of the CUs 16 in CBs 28a to28m. As described previously that interchange occurs periodically and itshould now be clear that that period is three milliseconds. In otherwords, every three milliseconds all of the CUs 16 in system 10 willreceive from and transmit to SPU 20 "new" signaling, provisioning andtesting information. The manner in which the SYNC signal is used incircuit 72 will be described in connection with FIG. 5d.

Before circuit 66 is further described, the transfer of signaling,provisioning, and testing information to and from CU 16 and SPU 20 willfirst be further described. That description will then be followed by afurther description of the transfer of PCM signals to and from CU 16 andTRU 18.

As before, it will be assumed that there are six bytes associated withthe signaling, provisioning and testing information for each of the twosubscribers served by CU 16. Digroup A of CB 28a (the digroup and CB inwhich CU 16 is assumed to be located) serves 24 subscribers and CB 28aserves 96 subscribers in total. Therefore every three milliseconds, 96×6or 576 bytes of signaling, provisioning and testing information istransferred to and from CB 28a and SPU 20.

As CU 16 serves the first and second channels of digroup A it receivesand transmits byte 1 (the first byte) for the first channel almostimmediately after the SYNC pulse has terminated. As there are separatepairs of RCUDLs and TCUDLs connected between each CB and SPU 20, all ofthe first channels of digroup A of each of CBs 28a to 28m receive andtransmit their first byte at the same time over the associated pairs ofR and T CUDLs.

Each byte of signaling, provisioning and testing information on RCUDL30a and TCUDL 31a contains eight bits and they are shown symbolically inFIG. 5b for the first channel of digroup A. It should be noted that eachbit has a time duration equal to the time for one cycle of the CLKsignal (approximately 0.65 microseconds). Each byte occupies its owntime slot which has a time duration equal to the time to send or receivethe eight bits in that byte (approximately 5.2 microseconds). The timeslot associated with the first channel of digroup A is also known as thefirst time slot as it is the one which occurs just after each SYNCpulse. FIG. 5b shows only the waveforms associated with that first timeslot.

As previously described the first byte of signaling, provisioning andtesting information associated with the first channel of digroup A isfollowed immediately by the first byte of such information associatedwith the second channel of digroup A. That second channel may be servedby CU 16 as was assumed for the purposes of this description or it maybe served by another one of the 12 CUs in digroup A. The particularchannels in each digroup A served by each CU is primarily a matter ofdesign choice.

Also as previously described all of the first bytes of such informationfor all of the 24 channels in digroup A are transferred to and from SPU20 in succession. In other words, the first 24 time slots after theoccurrence of the SYNC pulse are associated with the 24 first bytestransferred to and from the 12 CUs 16 in digroup A. Those 24 bytesconstitute in total 192 bits. PCM signals are transferred to and fromsubscriber end 12 in the form of frames, each of which is capable oftransferring the signals for 24 channels. Each frame is made up of 24eight bit bytes each of which is associated with a respective one of the24 channels plus one framing bit or 193 bits in total. The time fortransferring a frame is 125 microseconds. Therefore, the time totransfer all of the first bytes for the 24 channels in digroup A isessentially equal to the time for one frame.

All of the second, third, fourth, fifth and sixth bytes of informationfor the 24 channels in digroup A also each take one frame to betransferred. Therefore, it takes six frames to transfer all of the sixbytes of information for the 24 channels in digroup A. It also takes sixframes each to transfer all of the bytes of information for each ofdigroups B, C and D. In total it takes 24 frames to transfer all of thebytes of information for all of the CUs in each of CBs 28a to 28m. Aseach frame is equal in duration to 125 microseconds, the duration ofthose 24 frames is 3 milliseconds which is the time between occurrencesof each SYNC pulse.

The transfer of PCM signals to and from CU 16 and TRU 18 will now befurther described. PCM signals are transferred to and from subscriberend 12 and C.O. end 14 over each of the multiplicity of digitaltransmission lines 26a to 26m in the form of frames. Each frame iscapable of transferring the signals for 24 channels. As described aboveeach digroup serves 24 channels. Therefore, each of lines 26a to 26mtransfers the PCM signals for an associated one of the digroups.

Each of CBs 28a to 28m has four digroups. In order to transfer all ofthe PCM signals for the four digroups in each CB, four digitaltransmission lines must be used. In other words, lines 26a to 26m may besaid to be divided into groups of four lines each with each such groupbeing associated with a respective one of CBs 28a to 28m. System 10 hasa multiplicity of LIUs 24a to 24m. Each of LIUs 24a to 24m is associatedwith a respective one of the groups of four digital transmission linesand is therefore associated with a respective one of CBs 28a to 28m.

Each of the 24 channels served by each digroup has its own unique timeslot. The PCM signals for those 24 channels are transferred tosubscriber end 12 from C.O. end 14 and vice versa in a single frame,i.e. every 125 microseconds. As was described above it was assumed thatthe first time slot for the 24 channels in digroup A of CB 28a isassociated with the first channel in that digroup. The receive PCM(RPCM) signal for that time slot and the transmit PCM (TPCM) signal forthat time slot are both shown symbolically in FIG. 5b.

Referring once again to FIG. 5a it is seen that counting and decodecircuit 68 is connected by wires 74 to both PCM interface circuit 70 andCUDL interface circuit 72. Circuit 68 is also connected to circuit 72 byother wires 76. As has been described above, CU 16 serves two channelseach of which has its associated time slot for receiving andtransmitting PCM signals and for receiving and transmitting signaling,provisioning and testing information. Therefore, CU 16 must be told whenone of its two time slots is occurring and also which of the twochannels it serves is associated with that time slot.

Without that information, the CU would not "know" that there is receivesignaling, provisioning and testing information on RCUDL 30a for one ofthe channels it serves or that this is the time when it should transmitsuch information for that channel on TCUDL 31a. Without that informationthe CU would not "know" that there is a receive PCM signal on line 62a(1) for one of the channels it serves or that this is the time when itshould transmit a PCM signal for that channel on line 64a (1). Thatinformation regarding the occurrence of a time slot and the channel withwhich it is associated is provided by the signals on wires 74 for PCMinterface circuit 70 and by the signals on wires 74 and 76 for CUDLinterface circuit 72. The manner in which those signals are generatedwill be described in connection with FIG. 5c.

There is also shown in FIG. 5a wires 78 which connect PCM interfacecircuit 70 to a CODEC, i.e. coder-decoder (not shown). A CODEC, as iswell known in the art, is used to decode received PCM signals intoanalog signals and encode analog signals into PCM signals so that theycan be transmitted from CU 16 to TRU 18. CODECs are available inintegrated circuit chips from a variety of manufacturers as for examplethe TP3054 type chip available from National Semiconductor Corporation,Santa Clara, Calif.

Wires 78 carry the receive PCM signals for the two channels served by CU16 from interface circuit 70 to the CODEC and the PCM signals to betransmitted from those two channels to TRU 18 from the CODEC to theinterface circuit 70. Those signals contain eight bits, i.e. are onebyte, for each of the two channels and are shown symbolically in FIG. 5bfor the first channel in digroup A of CB 28a. The receive signal islabeled 78 RCV and the transmit signal is labeled 78 XMIT. As shown inFIG. 5b, the signal 78 XMIT starts one CLK signal cycle before thebeginning of the time slot in which it is to be transmitted, i.e. becomethe TPCM signal and the signal 78 RCV starts one CLK signal cycle afterthe beginning of the time slot in which it was received at CU 16 as theRPCM signal. As the RPCM and the 78 RCV signals are identical and as theTPCM and the 78 XMIT signals are identical it should be clear that PCMinterface circuit 70 introduces a delay to signals passing through itequal to the time for one cycle of the CLK signal.

Finally, circuit 68 is connected by wires 80 to the CODEC. In order toproperly perform its function of encoding and decoding PCM signals, theCODEC must know when the 78 RCV and 78 XMIT signals start for each ofthe two channels served by CU 16. Circuit 68 provides to the CODEC overthe wires 80, two pulses for each of the channels served by CU 16. Eachpulse has a time duration equal to the time for one cycle of the CLKsignal. One pulse occurs during the cycle of the CLK signal immediatelybefore the start of the 78 XMIT signal. That pulse tells the CODEC thatthe 78 XMIT signal will begin at the end of the pulse. It is shown inFIG. 5b for the first channel served by CU 16 and is labeled FSX. Theother pulse occurs during the cycle of the CLK signal immediately beforethe start of the 78 RCV signal. That pulse tells the CODEC that the 78RCV signal will begin at the end of the pulse. It is also shown in FIG.5 b for the first channel and is labeled FSR.

Referring now to FIG. 5c there is shown a more detailed block diagramfor counter and decode circuit 68. Circuit 68 includes counters 68a andchannel decode circuit 68b. Counters 68a includes four counters (notshown) and a circuit to detect the occurrence of the SYNC signal.

Each of the four counters in counter 68a will now be described in moredetail. The counters are:

i) a three bit counter which counts the eight (8) bits in each timeslot;

ii) a five bit counter which counts the 24 time slots that make up eachframe. This counter counts a time slot each time the three bit counterdescribed in i) counts the eight bits in each time slot. This counterskips the 193rd bit which occurs at the end of each frame, i.e. afterthe 24th time slot. The output signal of this counter is the channelcount (CHCT) signal and is connected to channel decode circuit 68b overwire 68c;

iii) another three bit counter which counts the six (6) framesassociated with the transfer of signaling, provisioning and testinginformation for the 24 channels in each of the four digroups in CB 28a.The output signal of this counter is the frame count (FRCT) signal andis connected by wires 76 to CUDL interface circuit 72; and

iv) a two bit counter which counts the four groups of six frames ofsignaling, provisioning and testing information associated with each CB.In effect, this counter identifies the digroup with which theinformation is associated. The output signal of this counter is thedigroup count (DICT) signal and is connected by wires 76 to the CUDLinterface circuit 72.

It should be appreciated that the four counters described above are allcounting occurrences of the CLK signal. In one embodiment of system 10the counters were clocked by the negative edge of the CLK signal. Theoccurrence of the SYNC signal resets all of the counters to zero.

The channel decode circuit 68b uses the CHCT signal in combination witha signal on wires 68d which represents the physical address (PHYS ADDR)of the CU 16 on which it is located to generate the signals which appearon wires 74. Each CU 16 has a unique physical address. That addressdepends solely on the particular card slot in which the CU card isinserted, i.e. its physical location in the digroup. It does not dependon the type of CU card. The address is not encoded on the card.

Each CU card has six pins which receive the address signals from thereceptacle into which the card is plugged. In system 10 each CU cardreceptacle in each digroup is given a unique physical address bygrounding appropriate ones of the six contacts in the receptacleassociated with the address signals. When a CU card is plugged into thatreceptacle it "learns" its physical address by decoding the PHYS ADDRsignal. While not shown in FIGS. 5a, 5c and 5d, CU 16 uses conventionallogic circuitry in a manner well known to those skilled in the art todecode its physical address.

The physical address identifies by number which two of the 24 channelsin the digroup the CU 16 serves and also which one of the four digroupsin CB 28a that CU 16 is located in. That is part of the informationwhich is decoded by the conventional logic circuitry described above.The CHCT signal is a count of the 24 channels in the digroup as theassociated time slots occur. The logic circuitry in circuit 68b (notshown) then simply compares the CHCT signal with the numbersrepresenting the two channels it serves. A first successful comparisonwill result in the generation of a first channel decode signal on wires74 and a second successful comparison will result in the generation of asecond channel decode signal on wires 74. For ease of description thatfirst channel decode signal is called ACD and the second channel decodesignal is called BCD.

For example, the CU 16 being described herein was assumed to serve thefirst and second channels of digroup A of CB 28a. When the time slot forthe first channel occurs the channel decode circuit 68b generates theACD signal to circuits 70 and 72. When the time slot for the secondchannel occurs the channel decode circuit 68b generates the BCD signalto circuits 70 and 72.

In a similar manner to the above, circuit 68b also includes decodingcircuitry (also not shown) responsive to the occurrence of the CHCTsignal and the physical address for generating the FSR and FSX signals.

Referring now to FIG. 5d there is shown a more detailed block diagramfor CUDL interface circuit 72. Circuit 72 includes CUDL decode circuit72a and a latch and shift register circuit 72b. CUDL decode circuit 72ais connected to receive the CLK signal, the SYNC signal, ACD and BCDsignals on wires 74 from channel decode circuit 68b and the FRCT andDICT signals on wires 76 from counters 68a.

As described above there are unique time slots associated with each ofthe two channels served by CU 16. In order that CU 16 receive andtransmit signaling, provisioning and testing information for thechannels it serves, the CU must "know" when a time slot is occurring forone of the channels it serves and also which of the two channels thattime slot is associated with. That information is provided to circuit72a by the FRCT, DICT, ACD and BCD signals.

The DICT signal identifies the digroup. As has been assumed throughoutthis description, CU 16 is in digroup A. CUDL decode circuit 72acontains logic circuitry which decodes the DICT signal to therebyprovide an enabling input to further logic circuitry when the A digroupis decoded. When the B, C and D digroups are decoded a disabling inputis provided to that further logic circuitry.

The FRCT signal identifies the frame. There are six frames associatedwith the 24 channels in digroup A. The six bytes of signaling,provisioning and testing information for each channel are eachassociated with a predetermined part of that information. For example,byte 1 may be associated with signaling information, bytes 2 and 3 maybe associated with various kinds of provisioning information and so on.Each of the six bytes for each channel served by CU 16 can be identifiedby the FRCT signal.

The ACD and BCD signals identify that a time slot associated with one ofthe two channels served by CU 16 is occurring. In this manner, circuit72 can load into latch and shift register circuit 72b only those byteson RCUDL 30a associated with the channels the CU 16 serves and transmiton TCUDL 31a only in those time slots associated with those channels.

There are up to 12 bytes of signaling, provisioning and testinginformation associated with the two channels served by CU 16. Those 12bytes comprise a total of up to 96 bits. Therefore, latch and shiftregister circuit 72b must have sufficient capacity to handle all of theinformation bits associated with the two channels, i.e. latch and shiftregister circuit 72b must have a capacity of up to 96 bits.

As described above the occurrence of a SYNC pulse every threemilliseconds provides a starting point for the next interchange ofsignaling, provisioning and testing information between CU 16 and SPU20. When that pulse occurs CUDL decode circuit 72a generates a signal tolatch and shift register circuit 72b so that the previously assembled 12bytes of signaling, provisioning and testing information to betransmitted to SPU 20 in the associated time slots during the threemilliseconds can be loaded in the shift register part of circuit 72b.That signal is called the latch load (LTLD) signal and is connected bywires 72c to circuit 72b.

As each time slot associated with the two channels served by CU 16occurs during the three millisecond time interval, CUDL decode circuit72a generates a clocking signal to circuit 72b. Circuit 72a generatesthe clocking signal by gating the CLK signal with the ACD and BCDsignals. The clocking signal is called the shift clocking (SCLK) signaland is connected by wire 72d to circuit 72b. As there are eight bitsassociated with each time slot, eight SCLK signals are provided tocircuit 72b for each such time slot. These eight SCLK signals cause thecircuit 72b to shift the bits stored therein one position for eachoccurrence of the eight SCLK signals. The information to be transmittedto SPU 20 is then shifted out of circuit 72b on to TCUDL 31a in groupsof eight bits each.

Simultaneously therewith the receive signaling, provisioning and testinginformation available on RCUDL 30a for that CU 16 during that time slotis shifted into the shift register part of circuit 72b one bit at atime. At the end of each three millisecond time interval all of the bitsloaded into the shift register part of circuit 72b at the beginning ofthe time interval for transmission to SPU 20 have been shifted out ofthe shift register part of circuit 72b and on to TCUDL 31a. During thattime interval the bits associated with the received signaling,provisioning and testing information on RCUDL 30a for that CU 16 havebeen loaded into the shift register part of circuit 72b. Therefore atthe end of the three millisecond time interval the shift register partof circuit 72b contains receive information for the two channels servedby CU 16.

Upon the next occurrence of the LTLD signal the receive information isdownloaded from the shift register to the latch part of circuit 72b. Theinformation to be transmitted to SPU 20 is then loaded into the shiftregister part of circuit 72b. It should be appreciated that thedownloading of the receive information into the latch part of circuit72b must occur in time before the loading of the transmit informationinto the shift register part of circuit 72b.

The use of the signaling, provisioning and testing information receivedby CU 16 will now be described. The manner in which such information isused depends on the particular type of channel unit card that CU 16 is.That in turn depends on the level of service provided to the subscribesserved by CU 16. For example, in one type of channel unit card used insystem 10, the provisioning information received at CU 16 is used tocontrol the gain in the transmit and receive directions for each of thetwo channels served by that CU. That type of channel unit card includesan amplifier having a number of resistors which can be selectivelygrounded to thereby set and/or change the gain. In one such embodimentof that channel unit type the gain can be set and/or changed inincrements of 0.1 db.

Another use of the received provisioning information may be to operateswitches on the channel unit card to thereby change the card from onewhich provides two wire E and M signaling to one which provides fourwire E and M signaling. As is well known to those in the art this typeof signaling is used in connection with trunk circuits.

One use of the testing information is to allow testing of a particularchannel unit card from the C.O. end 14 of system 10. The card may, forexample, include two solid state switches one of which is located inshunt relationship between the PCM interface circuit 70 and the CODECand the other which is located in shunt relationship between the CODECand the subscribers served by the channel unit card. In normal operationboth switches are open. The received testing information may cause thechannel unit card to be tested by closing the switch between circuit 70and the CODEC. In this manner PCM signals sent from C.O. end 14 to thechannel unit card are looped back to the C.O. end 14 without goingthrough the CODEC. The received testing information may also cause thechannel unit card to be tested by closing the switch located between theCODEC and the subscribers. In this manner, PCM signals received from theC.O. end 14 are decoded by the CODEC and are then looped back to theCODEC to be encoded into PCM signals and transmitted to the C.O. end 14.

The signaling information is used by CU 16 in the conventional mannerwell known in the art. For example, the received signaling informationmay indicate that there is a telephone call for either one or both ofthe two subscribers served by CU 16. Provided that the telephone of thecalled subscriber is on-hook, the signaling information will cause aringing generator located on the CU to be connected to ring thatsubscriber's telephone.

While not shown in FIGS. 5a, c or d it should be obvious that CU 16 mustinclude logic circuitry to decode the various possible combinations ofbits in each of the up to six bytes of signaling, provisioning andtesting information received at CU 16 for each of the two channelsserved by CU. The design of that decode circuitry depends on the type ofchannel unit card that CU 16 is.

There has been described a system 10 in which a subscriber end 12 and aC.O. end 14 are connected to each other by a multiplicity of digitaltransmission lines 26a to 26m. At each end of the system a multiplicityof LIUs 24a to 24m are connected to the lines 26a to 26m. The digitallyencoded signals on each of lines 26a to 26m are transmitted to andreceived from C.O. end 14 in a serial bit stream at the rate of 1.544Mbps. As has been previously described and as is well known in the art,these signals are in the form of frames each of which is capable oftransferring signals (encoded voice and signaling information) for 24channels. In each frame there are 24 eight bit bytes each of which isassociated with a respective one of the 24 channels. By convention, theleast significant bit in each byte in frames 6 and 12 is used totransfer signaling information rather than being used as part of theencoded voice.

As has been previously described each of LIUs 24a to 24m is associatedwith a respective one of groups of four lines each for lines 26a to 26m.For signals received from C.O. end 14 on the associated group of lineseach LIU must include circuitry which separates the signalinginformation in frames 6 and 12 from the encoded voice, i.e. disassemblesthe frame. For signals to be transmitted to C.O. end 14 on theassociated group of lines, each LIU must include circuitry whichcombines the signaling information with the encoded voice, i.e.assembles the frames. Such "framing" circuitry may be embodied in theform of an integrated circuit chip, such as the DS 2180 chip availablefrom Dallas Semiconductor, Dallas, Tex, which performs both the assemblyand dissassembly of the frames. As each LIU interfaces with four digitaltransmission lines it includes four such chips, each associated with arespective one of the lines.

It should be appreciated that as on each of lines 26a to 26m signals aretransferred in a serial bit stream at the rate of 1.544 Mbps that inorder for each LIU to interface with four such lines the framingcircuitry must operate at a frequency of 6.176 MHz, i.e. at four timesthe rate of occurrence of the CLK signal. Therefore, the PLL not onlygenerates the CLK signal but also a clock signal which occurs at a ratewhich is four times faster then the rate of occurrence of the CLKsignal. For ease of description the 6.176 MHz clock signal will bereferred to hereinafter as the fast clock (FCLK) signal.

A single transmission line connects all of the LIUs 24a to 24m to TRU18. All of the LIUs share that transmission line by transferring the PCMsignals received from or transmitted to C.O. end 14 in parallel on thatline, i.e. all eight bits of each byte are transferred simultaneously.Therefore, each of LIUs 24a to 24m must include a serial to parallelconverter for converting PCM signals received from C.O. end 14 from aserial bit stream to parallel prior to transmission to TRU 18 and aparallel to serial converter for converting PCM signals from TRU 18 to aserial bit stream prior to transmission to C.O. end 14.

In a similar manner a single transmission line connects all of the LIUs24a to 24m to SPU 20. All of the LIUs share that transmission line bytransferring the signaling information received from or transmitted toC.O. end 14 in a serial bit stream on that line. It is not necessary forthe signaling information to be transmitted in parallel between the LIUsand SPU 20 as the signaling information occurs only in frames 6 and 12and there is only one bit of signaling information for each of the 24channels in the frame.

As shown in FIGS. 3 and 4b both TRU 18 and SPU 20 include parallel toserial and serial to parallel converters. All transfer of PCM signalsbetween TRU 18 and the CUs 16 and all transfer of supervisoryinformation, i.e. signaling, provisioning and testing informationbetween SPU 20 and the CUs 16 occurs in the form of a serial bit stream.All transfer of PCM signals between the LIUs and TRU 18 occurs inparallel.

While TRU 18 and SPU 20 have been shown as having separate serial toparallel and parallel to serial converters and while LIUs 24a to 24mhave been described as having such separate converters it should beappreciated that both such converters may be embodied by a singleconverter which simultaneously performs both conversions. One embodimentfor such a converter is shown in FIG. 6. That embodiment is describedfor a single converter 80 which is assumed to be located in TRU 18. Indescribing that converter it is assumed that system 10 has seven LIUseach of which are connected by an associated one of seven groups of fourdigital transmission lines each to C.O. end 14, i.e. system 10 has 28digital transmission lines 26a to 26m. System 10 may also include one ormore spare LIUs which are each capable of being connected to any one ofthe seven groups of four lines each.

As has been described TRU 18 is connected by four lines to each of CBs28a to 28m. Each of the four lines are associated with a respective oneof the four digroups in each CB. In describing converter 80 it isassumed that system 10 has seven CBs, i.e. 28 lines are used to connectall of the CBs to TRU 18.

Referring now to FIG. 6 there is shown a block diagram for converter 80.Converter 80 has a multiplicity of horizontal shift registers 82 and amultiplicity of vertical shift registers 84. The registers 82 and 84 arein separate layers (not shown) with the horizontal registers 82 being inone layer and the vertical registers being in the other layer. For easeof illustration, converter 80 is shown in FIG. 6 with only twohorizontal and two vertical shift registers 82, 84.

The horizontal shift registers 82 are connected between a multiplicityof inputs 80a and a multiplicity of outputs 80b of converter 80. Inputs80a are connected to the associated one of the 28 PCM data lines 64a(1to 4) to 64m(1 to 4) over which PCM signals to be transmitted from CBs28a to 28m to C.O. end 14 are carried. Outputs 80b are connected to theassociated one of the 28 PCM data lines 62a(1 to 4) to 62m(1 to 4) overwhich PCM signals received from C.O. end 14 for CBs 28a to 28m arecarried. Converter 80 then has 28 horizontal shift registers 82 eachassociated with a respective one of the pairs of data lines 62a(1),64a(1) to 62m(4), 64m(4). Each horizontal register has an eight bitcapacity.

The vertical shift registers 84 are connected between the multiplicityof inputs 80c and the multiplicity of outputs 80d of converter 80.Inputs 80c and outputs 80d are both connected to the transmission linebetween TRU 18 and all of the LIUs over which the encoded voice PCMsignals received at the LIUs from C.O. end 14 or to be transmitted bythe LIUs to C.O. end 14 are transferred in parallel. Each of the inputs80c and the outputs 80d are associated with a respective one of theeight bits. Converter 80 then has eight vertical shift registers 84 eachof which has a 28 bit capacity.

As has been previously described, PCM signals are transferred betweenTRU 18 and all of the CUs 16 in a serial bit stream. In converter 80,transmit PCM signals from all of the CUs 16 are then clocked into the 28horizontal shift registers 82 one bit at a time at the rate of 1.544Mbps. Receive PCM signals from C.O. end 14 for all of the CUs 16 areclocked out of the 28 horizontal shift registers 82 one bit at a time atthe same rate.

As has been previously described, PCM signals are transferred betweenTRU 18 and all of the LIUs 24a to 24m in parallel. In converter 80,receive PCM signals from all of the LIUs, i.e. from C.O. end 14 areclocked into the eight vertical shift registers 84 by the FCLK signalone byte at a time at the rate of 6.176 Mbps. Transmit PCM signals fromTRU 18 to all of the LIUs are clocked out of the eight vertical shiftregisters 84 by the FCLK signal one byte at a time at the rate of 6.176Mbps.

The flow of PCM signals into and out of converter 80 will now bedescribed. For ease of description it will be assumed that all of thehorizontal and vertical registers 82, 84 are initially empty. PCMsignals are received at the seven LIUs from the C.O. end 14 on the 28transmission lines. The eight bits that constitute the byte received inthe first time slot on each of the 28 lines are transferred in parallelin a predetermined order to TRU 18 at the rate of 6.176 Mbps.

As has been previously described receive path 18a of TRU 18 performs thenecessary time slot interchanging for those signals. This interchangingis also performed at the rate of 6.176 Mbps. The time slot interchanged(TSI'd) receive PCM signals then arrive at inputs 80c of converter 80one byte at a time at the rate of 6.176 Mbps. The TSI'd receive PCMsignals are clocked into the eight vertical shift registers 84 at thatrate.

As each of the 28 TSI'd bytes are clocked into registers 84 thepreviously clocked in bytes are shifted one location in each of theregisters 84 closer to outputs 80d of converter 80. Each register 84 hasa 28 bit capacity. At the end of the time for one time slot (about 5.2microseconds) all 28 bytes received from C.O. end 14 have been clockedinto the eight registers 84 with the first such byte occupying thelocation in the registers closest to outputs 80d and the last such byteoccupying the location in the registers closest to inputs 80c. Actually,all 28 bytes have been clocked into registers 84 before the time for onetime slot has elapsed. The eight bits in each byte are clocked intoregisters 84 every 0.162 microseconds (the inverse of 6.176 Mbps). Ittakes 28 cycles of the FCLK signal (about 4.5 microseconds) to clock inall 28 bytes. The time for one time slot to occur is equal to 32 cyclesof the FCLK signal. During the last four cycles of the FCLK signal ineach time slot no further shifting takes place in registers 84.

Simultaneously, the PCM signals from CUs 16 for transmission to C.O. end14 have been clocked into horizontal shift registers 82. Those signalsappear at inputs 80a of converter 80 and are clocked into registers 82at the rate of 1.544 Mbps, i.e., one bit is clocked into registers 82every 0.65 microseconds (the inverse of 1.544 Mbps). At the end of thetime for one time slot all eight bits that are the first byte in thetransmit PCM signals are in registers 82 with the first bit in each byteoccupying the location closest to outputs 80b of converter 80.Therefore, at the end of the time for one time slot the receive TSI'dPCM signals for transmission to the CUs and the transmit PCM signalsfrom the CUs have been loaded into converter 80.

Outputs 80d of converter 80 are connected to the transmission line overwhich eight bits are simultaneously transferred in parallel to the LIUsfor transmission to C.O. end 14. Outputs 80b of converter 80 areconnected to the 28 data lines [62a(1 to 4) to 62m(1 to 4)] over whichserial bit streams are transferred to the CUs. The horizontal registers82 are connected between inputs 80a and outputs 80b. The verticalregisters 84 are connected between inputs 80c and outputs 80d. At theend of each time slot the contents of the vertical registers 84 shouldgo to the CUs and the contents of the horizontal registers 82 should goto the LIUs. To accomplish that result the contents of the two sets ofregisters 82, 84 are "flipped" at the end of each time slot, i.e. thecontents of registers 82 are placed in registers 84 and the contents ofregisters 84 are placed in registers 82.

During the next time slot new PCM signals for transmission to C.O. end14 are clocked into horizontal shift registers 82 one bit at a time atthe rate of 1.544 Mbps. At the same time the contents of those registersat the beginning of this time slot are shifted out one bit at a time atthe same rate. As a result of the flipping described above, the contentsof those registers at the beginning of this next time slot are TSI'd PCMsignals received in the last time slot. Therefore during each time slotas new PCM signals for transmission to C.O. end 14 are clocked intoregisters 82 at inputs 80a, the PCM signals received from C.O. end 14 inthe previous time slot are clocked out of registers 82 at outputs 80bfor transmission to the CUs.

Also during this next time slot, i.e. the time slot described above, newTSI'd PCM signals received from C.O. end 14 are clocked into registers84 one byte at a time at the rate of 6.176 Mbps. At the same time thecontents of those registers at the beginning of this next time slot areclocked out one byte at a time at the same rate. As a result of theflipping described above the contents of those registers at thebeginning of this next time slot are PCM signals for transmission toC.O. end 14 transmitted from the CUs 16 during the last time slot.Therefore during each time slot as new TSI'd PCM signals received fromC.O. end 14 are clocked into registers 84 at inputs 80c, the PCM signalstransmitted from the CUs 16 during the last time slot are clocked out ofregisters 84 at outputs 80d for time slot interchanging in TRU 18 andsubsequent transmission to C.O. end 14.

It should be appreciated that in system 10, TRU 18 provides time slotinterchanging in both the receive and transmit directions for the PCMsignals representing encoded voice. The ability of TRU 18 to providethat time slot interchanging in the receive direction results from theinformation stored in connection RAM 52 and in the transmit directionresults from the information stored in connection RAM 60. It should alsobe appreciated that in system 10, SPU 20 provides time slotinterchanging in both the receive and transmit directions for thesignaling information. The ability of SPU 20 to provide that time slotinterchanging in the receive direction results from the informationstored in connection RAM 32 and in the transmit direction results fromthe information stored in connection RAM 40. It should further beappreciated that in system 10, SPU 20 also provides interchanging ofsignaling state formats in both the transmit and receive directions forthe signaling information. The ability of SPU 20 to provide thatinterchanging of signaling state formats in the receive directionresults from the information stored in translation RAM 34 and in thetransmit direction results from the information stored in translationRAM 42.

There is given below a listing for the routines contained in CPU 22 forperforming various calculations relating to the time slot interchangingdescribed above. The listing has a total of 12 pages. While CPU 22 mayhave to execute additional software to accomplish the functionsdescribed above, listings for that software are not included. The formthat that software should take would, in view of that description, beobvious to one skilled in the art.

It is to be understood that the description of the preferred embodimentis intended to be only illustrative, rather than exhaustive, of thepresent invention. Those of ordinary skill will be able to make certainadditions, deletions, and/or modifications to the embodiment of thedisclosed subject matter without departing from the spirit of theinvention or its scope, as defined by the appended claims. ##SPC1##

What is claimed is:
 1. In a digital transmission system for providingservice to a multiplicity of subscribers by a multiplicity of channelunits, said system having two terminals interconnected to each other bytransmission means, said transmission means carrying supervisory andnonsupervisory information for each of said channel units from one ofsaid terminals to the other of said terminals and from said otherterminal to said one terminal, said one terminal comprising:at least onechannel bank having one or more of said channel units, each of saidchannel units associated with a predetermined number of saidsubscribers; interface means connected to said transmission means forreceiving said supervisory and nonsupervisory information from saidother terminal to said one terminal and for transmitting to said otherterminal said supervisory and nonsupervisory information from said oneterminal; a first single data line connected between said interfacemeans and said at least one channel bank, said first single data linefor carrying from said interface means to said at least one channel bankall of said supervisory information from said other terminal for said atleast one channel bank and not for carrying from said interface means tosaid at least one channel bank any of said nonsupervisory informationfrom said other terminal for said at least one channel bank; and asecond single data line connected between said interface means and saidat least one channel bank, said second single data line for carryingfrom said at least one channel bank to said interface means all of saidsupervisory information from said at least one channel bank for saidother terminal and not for carrying from said at least one channel bankto said interface means any of said nonsupervisory information from saidat least one channel bank for said other terminal.
 2. The one terminalof claim 1 further comprising:another channel bank having another one ormore of said channel units, each of said channel units associated with apredetermined number of said subscribers; a third single data lineconnected between said interface means and said another channel bank,said third single data line for carrying from said interface means tosaid another channel bank all of said supervisory information from saidother terminal for said another channel bank and not for carrying fromsaid interface means to said another channel bank any of saidnonsupervisory information from said other terminal for said anotherchannel bank; and a fourth single data line connected between saidinterface means and said another channel bank, said fourth single dataline for carrying from said another channel bank to said interface meansall of said supervisory information from said another channel bank forsaid other terminal and not for carrying from said another channel bankto said interface means any of said nonsupervisory information from saidanother channel bank for said other terminal.
 3. The one terminal ofclaim 1 wherein said supervisory information includes signalinginformation for said subscribers and said interface meanscomprises:first means connected to said transmission means for receivingsaid signaling information in a first information sequence order fromsaid other terminal and for transmitting to said other terminal saidsignaling information in said first information sequence order; andsecond means connected between said first means and said first andsecond single data lines for interchanging said signaling informationfrom said other terminal from said first information sequence order to asecond information sequence order and said signaling information forsaid other terminal from said second information sequence order to saidfirst information sequence order, said first single data line carryingin said second information sequence order all of said signalinginformation for said at least one channel bank and said second singledata line carrying in said second information sequence order all of saidsignaling information from said at least one channel bank.
 4. The oneterminal of claim 3 wherein said first means receives said signalinginformation from said other terminal in a first format and transmitssaid signaling information to said other terminal in said first formatand said first data line carries all of said signaling information forsaid of at least one channel bank in a second format and said seconddata line carries all of said signaling information from said at leastone channel bank in said second format and said second means also forconverting all of said signaling information for said at least onechannel bank from said first format to said second format and all ofsaid signaling information from said at least one channel bank from saidsecond format to said first format.
 5. The one terminal of claim 1wherein said nonsupervisory information and said supervisory informationare carried on said transmission means as digital signals having apredetermined transmission bit rate, said one terminal interface meansis also for generating signals related to said bit rate from saiddigital signals.
 6. The one terminal of claim 5 further comprising meansconnected between said interface means and said at least one channelbank for carrying from said interface means to said at least one channelbank said bit rate related signals and wherein each of said at least onechannel units comprises:means responsive to said bit rate relatedsignals for determining when supervisory information related to each ofsaid predetermined number of said subscribers is occurring on said firstdata line and for which one of said subscribers and generating signalsindicative thereof; and interface means connected to said first dataline responsive to said signals indicative of when related supervisoryinformation is occurring and for which one of said subscribers and saidbit rate related signals for selecting from said first data line onlysupervisory information related to each of said predetermined number ofsaid subscribers.
 7. The one terminal of claim 6 wherein each of saidchannel unit 3 interface means is also connected to said second dataline and is responsive to said supervisory information indicativesignals for placing on said second data line all of said supervisoryinformation related to said predetermined number of subscribers servedby said channel unit.
 8. The one terminal of claim 1 wherein saidsupervisory information includes signaling information for saidsubscribers and said interface means comprises:first means connected tosaid transmission means for receiving said signaling information in afirst format from said other terminal and for transmitting to said otherterminal said signaling information in said first format; and secondmeans connected between said first means and said first and said secondsingle data lines for converting all of said signaling information fromsaid other terminal from said first format to a second format and all ofsaid signaling information for said other terminal from said secondformat to said first format, said first single data line carrying insaid second format all of said signaling information for said at leastone channel bank and said second single data line carrying in saidsecond format all of said signaling information from said at least onechannel bank.
 9. The one terminal of claim 8 wherein said supervisoryinformation also includes said second format information, saidconverting means including means for storing said second formatinformation therein.
 10. The one terminal of claim 9 wherein saidinterface means further comprises means responsive to said second formatinformation for controlling said converting means storage means forstoring said second format information therein.
 11. The one terminal ofclaim 3 wherein said supervisory information also includes said secondorder information, said second means including means for storing saidsecond order information therein.
 12. The one terminal of claim 11wherein said interface means further comprises means responsive to saidsecond order information for controlling said second means storage meansfor storing said second order information therein.
 13. In a digitaltransmission system for providing service to a multiplicity ofsubscribers, each of said subscribers having an associated predeterminedformat for signaling information which may be different from each other,said system having two terminals interconnected to each other bytransmission means, said transmission means carrying for all of saidsubscribers signaling information from one of said terminals to theother of said terminals, said transmission means carried signalinginformation having for each of said subscribers an associated formatwhich may be different than said predetermined format associated witheach of said subscribers, said other terminal comprising:a) interfacemeans connected to said transmission means for receiving all of saidsignaling information carried on said transmission means; b) meansresponsive to all of said transmission means carried signalinginformation received by said interface means for translating for each ofsaid subscribers said transmission means carried signaling informationformat associated with each of said subscribers to said predeterminedsignaling information format associated with each of said subscribers;and c) means connected between said translating means and all of saidsubscribers for carrying from said translating means to all of saidsubscribers all of said received signaling information in saidassociated predetermined format.
 14. The other terminal of claim 13wherein said translating means comprises:i) a data storage means havinga multiplicity of locations each associated with a respective one ofsaid subscribers, each of said locations storing for said associatedsubscriber said associated predetermined format; and ii) meansresponsive to said transmission means carried signaling information foreach one of said multiplicity of subscribers for addressing saidassociated respective one of said data storage means multiplicity oflocations to read out said associated predetermined format storedtherein.
 15. The other terminal of claim 14 wherein said means connectedbetween said translating means and all of said subscribers also carriesfrom all of said subscribers to said translating means signalinginformation in said associated predetermined format transmitted from allof said subscribers and said translating means is responsive to all ofsaid subscriber transmitted signaling information for translating foreach of said subscribers said transmitted predetermined signaling formatassociated with each of said subscribers to said transmission meanscarried signaling information format associated with each of saidsubscribers.
 16. The other terminal of claim 13 wherein each of saidsubscribers also have an associated predetermined time slot for saidsignaling information and said transmission means carried signalinginformation also has for each of said subscribers an associated timeslot which may be different from said predetermined time slot and saidtranslating means is also responsive to all of said signalinginformation for interchanging for all of said subscribers saidtransmission means carried signaling information time slot associatedwith each of said subscribers to said predetermined time slot associatedwith each of said subscribers and said means connected between saidtranslating means and all of said subscribers also carries to all ofsaid subscribers said received signaling information in saidpredetermined time slot associated with each of said subscribers. 17.The other terminal of claim 13 further comprising:i) a multiplicity ofchannel units for serving said multiplicity of subscribers; and ii) achannel bank having one or more of said channel units, each of saidchannel units associated with a predetermined number of saidsubscribers;and said means connected between said translating means andall of said subscribers includes a first data line connected betweensaid translating means and said at least one channel bank for carryingto said at least one channel bank all of said received signalinginformation for said at least one channel bank in said associatedpredetermined format.
 18. The other terminal of claim 15 furthercomprising:i) a multiplicity of channel units for serving saidmultiplicity of subscribers; and ii) a channel bank having one or moreof said channel units, each of said channel units associated with apredetermined number of said subscribers;and said means connectedbetween said translating means and all of said subscribers comprises: i)a first data line connected between said translating means and said atleast one channel bank for carrying to said at least one channel bankall of said received signaling information for said at least one channelbank in said associated predetermined format; and ii) a second data lineconnected between said translating means and said at least one channelbank for carrying from said at least one channel bank all of saidtransmitted signaling information from said at least one channel bank insaid associated predetermined format.
 19. In a digital transmissionsystem for providing service to a multiplicity of subscribers, each ofsaid subscribers having an associated predetermined time slot forsignaling information and an associated predetermined time slot fornonsupervisory information, said system having two terminalsinterconnected to each other by transmission means, said transmissionmeans carrying for all of said subscribers signaling and nonsupervisoryinformation from one of said terminals to the other of said terminals,said transmission means carried signaling information having for each ofsaid subscribers an associated time slot which may be different thansaid predetermined signaling information time slot associated with eachof said subscribers and said transmission means carried nonsupervisoryinformation having for each of said subscribers an associated time slotwhich may be different from said predetermined nonsupervisoryinformation time slot associated with each of said subscribers, saidother terminal comprising:a) interface means connected to saidtransmission means for receiving all of said signaling andnonsupervisory information carried on said transmission means for all ofsaid subscribers; b) means responsive to all of said transmission meanscarried signaling and nonsupervisory information received by saidinterface means for interchanging for all of said subscribers:i) saidtransmission means carried signaling information time slot associatedwith each of said subscribers to said predetermined signalinginformation time slot associated with each of said subscribers; and ii)said transmission means carried nonsupervisory information time slotassociated with each of said subscribers to said predeterminednonsupervisory information time slot associated with each of saidsubscribers; and c) means connected between said interchanging means andall of said subscribers for carrying from said interchanging means toall of said subscribers all of said received signaling information insaid associated predetermined time slot for signaling information andnot for carrying from said interchanging means to all of saidsubscribers any of said received nonsupervisory information.
 20. Theother terminal of claim 19 wherein said interchanging means comprises:i)first means responsive only to all of said received signalinginformation for interchanging for each of said subscribers saidtransmission means carried signaling information time slot associatedwith each of said subscribers to said predetermined signalinginformation time slot associated with each of said subscribers; and ii)second means responsive only to all of said received nonsupervisoryinformation for interchanging for each of said subscribers saidtransmission means carried nonsupervisory information time slotassociated with each of said subscribers to said predeterminednonsupervisory information time slot associated with each of saidsubscribers.
 21. The other terminal of claim 20 wherein each of saidsubscribers also has an associated predetermined format for saidsignaling information and said transmission means carried signalinginformation also has for each of said subscribers an associated formatwhich may be different from said predetermined format and said firstinterchanging means is also responsive to all of received signalinginformation for translating for all of said subscribers saidtransmission means carried signaling information format for each of saidsubscribers to said predetermined signaling information formatassociated with each of said subscribers and said means connectedbetween said interchanging means and all of said subscribers alsocarries to all of said subscribers said received signaling informationin said predetermined format associated with each of said subscribers.22. The other terminal of claim 21 further comprising:i) a multiplicityof channel units for serving said multiplicity of subscribers; and ii) achannel bank having one or more of said channel units, each of saidchannel units associated with a predetermined number of saidsubscribers;and said means connected between said interchanging meansand all of said subscribers comprises a first data line connectedbetween said first interchanging means and said at least one channelbank for only carrying to said at least one channel bank all of saidreceived signaling information for said at least one channel bank insaid associated predetermined format and in said associatedpredetermined time slot.
 23. In a digital transmission system forproviding service to a first multiplicity of subscribers by a firstmultiplicity of channel units, each of said channel units associatedwith a predetermined number of said subscribers, said system having twoterminals interconnected to each other by transmission means, saidtransmission means carrying supervisory and nonsupervisory informationfor each of said first multiplicity of subscribers as digital signalshaving a predetermined transmission bit rate from one of said terminalsto the other of said terminals, said other terminal including:i)interface means connected to said transmission means for receiving saidsupervisory and nonsupervisory information from said one terminal tosaid other terminal, said interface means responsive to said digitalsignals for generating signals related to said bit rate; ii) a firstsingle data line connected between said interface means and all of saidfirst multiplicity of channel units for carrying from said interfacemeans to all of said first multiplicity of channel units all of saidsupervisory information from said one terminal for each of said firstmultiplicity of subscribers and not for carrying from said interfacemeans to all of said first multiplicity of channel units any of saidnonsupervisory information from said one terminal for each of saidmultiplicity of subscribers; and iii) means connected between saidinterface means and all of said first multiplicity of channel units forcarrying from said interface means to said first multiplicity of channelunits said bit rate related signals,each of said first multiplicity ofchannel units comprising:a) means responsive to said bit rate relatedsignals for determining when supervisory information related to each ofsaid predetermined number of said first multiplicity of subscribers isoccurring on said first single data line and for which one of saidsubscribers and generating signals indicative thereof; and b) interfacemeans connected to said first single data line responsive to saidsignals indicative of when supervisory related information is occurringand for which one of said subscribers and said bit rate related signalsfor selecting from said first single data line only supervisoryinformation related to each of said predetermined number of said firstmultiplicity of subscribers served by said channel unit.
 24. The channelunit of claim 23 wherein said transmission means also carriessupervisory and nonsupervisory information from each of said firstmultiplicity of channel units from said other terminal to said oneterminal and said other terminal also includes a second single data lineconnected between said interface means and all of said firstmultiplicity of channel units, said second single data line for carryingfrom all of said first multiplicity of channel units to said interfacemeans all of said supervisory information from each of said firstmultiplicity of subscribers for said one terminal and not for carryingfrom all of said first multiplicity of channel units to said interfacemeans any of said nonsupervisory information from all of said firstmultiplicity of subscribers for said one terminal, andeach of said firstmultiplicity of channel units interface means is also connected to saidsecond data line and is responsive to said indicative signals forplacing on said second data line all of said supervisory informationrelated to said predetermined number of said first multiplicity ofsubscribers served by said channel unit.
 25. The channel unit of claim23 wherein said other terminal also includes a first transmission lineconnected between said interface means and all of said firstmultiplicity of channel units for carrying from said interface means toall of said first multiplicity of channel units all of saidnonsupervisory information from said one terminal for each of said firstmultiplicity of channel units and not for carrying from saidinterchanging means to all of said first multiplicity of channel unitsany of said supervisory information from said one terminal for each ofsaid first multiplicity of channel units, andwherein for each of saidchannel unitsi) said means responsive to said bit rate related signalsalso for determining when nonsupervisory information related to each ofsaid predetermined number of said first multiplicity of subscribers isoccurring on said first transmission line and for which one of saidsubscribers and generating signals indicative thereof; and ii) saidinterface means is also connected to said first transmission line and isalso responsive to said signals indicative of when nonsupervisoryinformation is occurring and for which one of said subscribers and saidbit rate related signals for selecting from said first transmission lineonly nonsupervisory information related to each of said predeterminednumber of said first multiplicity of subscribers served by said channelunit.
 26. In the system of claim 25 wherein said system provides serviceto a second multiplicity of subscribers by a second multiplicity ofchannel units, each of said second multiplicity of channel unitsassociated with a predetermined number of said second multiplicity ofsubscribers, said transmission means also carrying as said digitalsignals having said predetermined bit rate supervisory andnonsupervisory information for each of said second multiplicity ofsubscribers from said one terminal to said other terminal, said otherterminal interface means also for receiving said supervisory andnonsupervisory information for said second multiplicity of subscribersfrom said one terminal to said other terminal and said other terminalmeans for carrying said bit rate related signals from said interfacemeans to said first multiplicity of channel units also for carrying saidbit rate related signals to said second multiplicity of channel unitsand said other terminal further including a second single data lineconnected between said interface means and all of said secondmultiplicity of channel units for carrying from said interface means toall of said second multiplicity of channel units all of said supervisoryinformation from said one terminal for each of said second multiplicityof subscribers and not for carrying from said interface means to all ofsaid second multiplicity of channel units any of said nonsupervisoryinformation from said one terminal for each of said second multiplicityof subscribers,each of said second multiplicity of channel unitscomprising:a) means responsive to said bit rate related signals fordetermining when supervisory information related to each of saidpredetermined number of said second multiplicity of subscribers isoccurring on said second single data line and for which one of saidsubscribers and generating signals indicative thereof; and b) interfacemeans connected to said second single data line responsive to saidsignals indicative of when supervisory related information is occurringand for which one of said subscribers and said bit rate related signalsfor selecting from said second single data line only supervisoryinformation related to each of said predetermined number of said secondmultiplicity of subscribers served by said second channel unit.
 27. In adigital transmission system for providing service to a multiplicity ofsubscribers by a multiplicity of channel units, said system having twoterminals interconnected to each other by transmission means, saidtransmission means carrying supervisory and nonsupervisory informationfor each of said multiplicity of subscribers as digital signals having apredetermined transmission bit rate from one of said terminals to theother of said terminals, said other terminal including:i) at least onechannel bank having one or more of said channel units, each of saidchannel units associated with a predetermined number of saidsubscribers; ii) interface means connected to said transmission meansfor receiving said supervisory and nonsupervisory information from saidone terminal to said other terminal, said interface means responsive tosaid digital signals for generating signals related to said bit rate;iii) a first single data line connected between said interface means andsaid at least one channel bank for carrying from said interface means tosaid at least one channel bank all of said supervisory information fromsaid one terminal for each of said subscribers served by said at leastone channel bank and not for carrying from said interface means to saidat least one channel bank any of said nonsupervisory information fromsaid one terminal for each of said subscribers served by said at leastone channel bank; and iv) means connected between said interface meansand said at least one channel bank for carrying from said interfacemeans to said at least one channel bank said bit rate relatedsignals,each of said one or more channel units comprising:a) meansresponsive to said bit rate related signals for determining whensupervisory information related to each of said predetermined number ofsaid subscribers is occurring on said first single data line and forwhich one of said subscribers and generating signals indicative thereof;and b) interface means connected to said first single data lineresponsive to said signals indicative of when supervisory relatedinformation is occurring and for which one of said subscribers and saidbit rate related signals for selecting from said first single data lineonly supervisory information related to each of said predeterminednumber of said subscribers served by said channel unit.